VLSI Fast-Switching Implementation in the Programmable Cycle Generator for High-Speed Operation

摘要

This paper proposes a two-delay line, and a time-to-digital detector allows the pulse width-control circuit to operate over a large frequency range including less delay cells. This paper presents a new duty cycle without the need for a look-up table. The CPI circuit blocks the reference clock to save the results of D flip-flops and reduce the dynamic power. It requires 6-8 clock cycles needed for an operating time of the processor of Intel(R) Core(TM) 2 Duo Processor. The proposed circuit performs well for an output duty cycle ranges from 30 to 70%. The operating frequency range is 264.089 MHz, and the estimated power is 108 mW.