A Low Power Consumption 65-nm CMOS True Time Delay N-path Circuit Achieving 2 ps Delay Resolution

摘要

Integrated true time delay cells are usually large in size, and have high relative delay variation. Here, the true time delay N-path topology is explored, where the signal is under-sampled with a number of parallel S/H circuits, and reconstructed and summed after a given time delay. The proposed circuit provides minimum resolution in time delay, while requiring relatively small area and power. The effect of the true time delay is analyzed with a linear periodic time-variant mathematical model, and is verified through measurements. Measurements of 65-nm CMOS chip implementation show up to 2 ns delay for bandwidth of 400 MHz, with maximum delay variation over frequency of 14 ps, delay resolution of 2 ps and power consumption of 9.6 mW.