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10.7 A 64GS/s 4×-Interpolated 1b Semi-Digital FIR DAC for Wideband Calibration and BIST of RF-Sampling A/D Converters

机译:10.7 64GS / s 4× - 用于宽带校准和RF采样A / D转换器的BIST的半数字FIR DAC

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The integration of complex DSP functions together with the entire RF-frontend enables software-defined base-station radio and mandates the availability of power-efficient and compact data converters in advanced digital CMOS processes. In a self-calibrated RF-sampling ADC-system, a co-integrated digital non-linear post-equalizer (NLEQ) can substantially increase the receiver performance [1], but wideband ADC-calibration also requires a wideband, calibration-free and ultra-linear reference signal source to train the NLEQ-coefficients during a dedicated calibration period, for example at startup, or during maintenance intervals. Another function with renewed importance in complex transceiver systems is the analog built-in-self-test (aBIST) capability [2] to spot-check the performance of data converters and RF-frontend building blocks, for example during scheduled test intervals in the field. In this work, a single-bit calibration-DAC (CALDAC), capable of wideband reference signal and linear sinewave generation at fclk/4 for these applications is presented. With fclk $=16$ GHz and $4 imes-$ interpolation, the CALDAC effectively samples at 64GS/s and implements a semi-digital FIR-architecture [3] –[5].
机译:复杂DSP功能的集成以及整个RF-Frentend一起实现了软件定义的基站无线电,并在高级数字CMOS过程中授权高功率和紧凑数据转换器的可用性。在自校准的RF样品ADC系统中,共同集成数字非线性均衡器(NLEQ)可以大大增加接收器性能[1],但宽带ADC校准也需要宽带,无校准和无校准超线性参考信号源在专用校准时段期间训练NLEQ系数,例如在启动时或在维护间隔期间。另一个功能在复杂的收发器系统中更新重要性是模拟内置的自检(安息)能力[2],以发现数据转换器和RF-Frentend构建块的性能,例如在预定的测试间隔期间场地。在这项工作中,提出了一种能够在FCLK / 4上提供宽带参考信号和线性正弦波的单位校准-DAC(Caldac),用于这些应用程序。使用FCLK $ = 16 $ GHz和4美元 Times-$插值,Caldac有效地以64gs / s采样,实现半数字杉木结构[3] - [5]。

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