Efficient Argument Range Reduction for Implementation of Double-Precision Floating-Point Exponential Function

摘要

Argument in implementing exponential function is often limited to fraction range by table look-up or range reducing method, so that radix-2 digit-recurrence algorithm or polynomial approximation can be used for evaluation exponential function. For double-precision floating-point exponential calculation, table look-up need many resources, while range reduction method available would lead to large delay, and occupy floating-point multiplier. Based on inherent properties of exponent operation, the main idea of this study is to simplify circuit design by considering the different contribution of all bits to reduce argument range, and eliminating those bit positions with a zero in the above contribution values. We discuss the algorithm, the implementation, and perform a rough comparison with typical design available, which indicates that the proposed implementation presents better trade-off between hardware complexity and latency than those available in the case of not requiring floating-point multiplier.