IEEE recommended practice for powering and grounding electronic equipment. (Color Book Series - Emerald Book)

摘要

Algorithms in digital signal processing (DSP) impose tight timingconstraints that the compiler has to respect while considering thelimited capacity of the available register files in a target DSPprocessor. Traditional code generation methods that schedule spill codeto satisfy storage capacity may take many iterations and are usually notcapable of satisfying the timing constraints. In this paper we present anew method to handle register file capacity constraints duringscheduling. The method identifies potential bottlenecks for registerbinding and subsequently serializes the lifetimes of values until it canbe guaranteed that all capacity constraints will be satisfied afterscheduling. Experiments show that we efficiently obtain high qualityinstruction schedules for DSP kernels