IEEE recommended practice for powering and grounding electronic equipment. (Color Book Series - Emerald Book)

摘要

This paper presents new techniques for architecture andperformance driven compilation of SW programs into RW (reconfigurableHW). These new techniques effectively improve on the complex resourcesharing approaches typical of high-level synthesis algorithms, which areefficient for layout flexible ASICs but are clearly not adequate forreconfigurable devices with predefined architectures. The compilationflow takes advantage of a specialized library of circuit-generators andonly resorts to logic synthesis for the generation of the data-path'scontrol unit. The algorithms under development are being integrated ontoan HW compiler that accepts programs previously compiled to JavaTM Bytecodes. A series of experiments has been performed using anumber of practical examples and the results achieved so far are verypromising and indicate that the RW compilation techniques proposed canprovide significant improvements over currently available methods