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Yield model characterization for analog integrated circuit using Pareto-optimal surface

机译:使用帕累托最优表面的模拟集成电路的良率模型表征

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A novel technique is proposed in this paper that achieves a yield optimized design from a set of optimal performance points on the Pareto front. Trade-offs among performance functions are explored through multi-objective optimization and Monte Carlo simulation is used to find the design point producing the best overall yield. One advantage of the approach presented is a reduction in the computational cost normally associated with Monte Carlo simulation. The technique offers a yield optimized robust circuit design solution with transistor level accuracy. An example using an OTA is presented to demonstrate the effectiveness of the work.
机译:本文提出了一种新颖的技术,该技术从Pareto前端的一组最佳性能点实现了成品率优化设计。通过多目标优化来探索性能函数之间的取舍,并使用蒙特卡洛模拟来找到产生最佳总体良率的设计点。提出的方法的一个优点是减少了通常与蒙特卡洛模拟相关的计算成本。该技术提供了具有晶体管级精度的良率优化的稳健电路设计解决方案。给出了使用OTA的示例,以演示工作的有效性。

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