Interconnect capacitances, crosstalk, and signal delay invertically integrated circuits

摘要

The impact of the three-dimensional circuit structure inVertically Integrated Circuits (VICs) on interconnect capacitances,crosstalk and signal delay is investigated based on measurements andsimulations. In comparison with planar IC technologies, increasedsubstrate coupling and reduced coupling capacitances between adjacentinterconnection lines considerably improve the noise immunity for VICswith chiplayers fabricated in silicon-bulk technology. For thin-filmsilicon-on-insulator chiplayers, noise immunity can be assured throughthe integration of conductive layers between active chips. The reducedinterconnection lengths at system level lead to decreased interconnectdelays despite higher total interconnect capacitances