Designing mixed-mode test pattern generators for minimum-overheadself-testing VLSI circuits

摘要

A simple technique for designing self-testable VLSI circuits,characterized by low silicon area overhead and maximum testing speed, isproposed. An original feature of this built-in self-test designtechnique is a procedure for synthesis of test pattern generators. Itsobjective is to design mixed-mode generators of minimal complexity thatmaximize the fault-sensitizing capabilities of test sequences producedwithin the allowable test running time. The approach does not requirethat any internal register of the original circuit be modified, and thebuilt-in test control logic is extremely simple. Applying test patternson consecutive clock cycles with the normal-operation clock frequencyleads to substantial enhancement of dynamic fault-detection capabilities