DelaY: An Efficient Tool for Retiming with Realistic Delay Modeling

摘要

The retiming transformation can be used to optimize synchronous circuits for maximum speed of operation by relocating their storage elements. In this paper, we describe DelaY, a tool for retiming edge-triggered circuits under a realistic delay model that handles load-dependent gate delays, variable register setup times, interconnect delays, and clock skew. The operation of DelaY relies on a novel linear programming formulation of the retiming problem in this model. For the special case where clock skew is monotonic and all registers have equal propagation delays, the retiming algorithm in our tool runs in polynomial time and can transform any given edge-triggered circuit to achieve a specifi clock period in O(V3F) steps, where V is the number of logic gates in the circuit and F is bounded by the number of registers in the circuit.