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Behavioral Synthesis Methodology for HDL-Based Specification and Validation

机译:基于HDL的规范和验证的行为综合方法

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This paper describes a HDL synthesis based design methodology that supports user adoption of behavioral-level synthesis into normal design practices. The use of these techniques increases understanding of the HDL descriptions before synthesis, and makes the comparison of pre- and post-synthesis design behavior through simulation much more direct. This increases user confidence that the specification does what the user wants, i.e. that the synthesized design matches the specification in the ways that are important to the user. At the same time, the methodology gives the user a powerful set of tools to specify complex interface timing, while preserving a user's ability to delegate decision-making authority to software in those cases where the user does not wish to restrict the options available to the synthesis algorithms.
机译:本文介绍了一种基于HDL综合的设计方法,该方法支持用户将行为级综合纳入正常的设计实践中。这些技术的使用增加了对合成之前的HDL描述的理解,并使通过仿真进行的合成前和合成后设计行为的比较更加直接。这增加了用户对规范满足用户需求的信心,即,合成设计以对用户重要的方式与规范相匹配。同时,该方法为用户提供了一组功能强大的工具,用于指定复杂的接口时序,同时在用户不希望限制可用于软件的选项的情况下,保留了用户将决策权限委派给软件的能力。综合算法。

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