On the modulo 2n+1 multiplication for diminished-1 operands

摘要

In this work we propose an enhancement to one of the most efficient modulo 2n +1 multipliers for diminished-1 operands already published. This improvement is achieved by reducing the partial products from n + 3 to n +1 . The derived partial products are reduced by a tree carry save adder architecture to two operands, which are finally added by a modulo 2n +1 diminished-1 adder. Our multipliers compared to existing implementations offer enhanced operation speed and have reduced area complexity.