This paper describes the implementation of a Euclidean squaredclassifier with a charge based synaptic matrix and discriminator, basedon a previously implemented Hamming classifier. The discriminatorcircuit is a generalized n-port version of the two-port differentialcharge-sensing amplifier that is conventionally used in DRAM's forbitline sensing. Both the quantifier and discriminator are implementedby charge based techniques, granting the simultaneous availability ofhigh integration density, low power consumption and high speed. Theanalog-to-digital (A/D) implementation was chosen to illustrate thenetwork's classification characteristics, since A/D conversion can beinterpreted as classifying an input in terms of A/D quantization levels.A detailed analysis of the classifier configuration is presented. Designissues are addressed at both the system and circuit levels, and somelimitations are identified. Simulation results of the the circuitconfirming its theoretical performance are presented, as well asmeasurements of the implemented chip. The circuit occupies an area of500 μm×250 μm, operates with a single 5 V power supply, andconsumes less than 1 mW of static power
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