Parallel implementation of image classifier architectures usingtransputer arrays

摘要

This paper considers fundamental issues with respect to aparticular type of classifier architecture (based on a cellular array oflogical processors forming a memory network) and investigates andassesses experimentally the relationship between the internal structureof the classifier and the implementational infrastructure realised interms of a transputer array. The memory network pattern classifierarchitecture based on binary feature (e.g. pixel level) samplingconsists of an array of memory cells for each possible pattern class,each cell associated with a feature which is related to an ordered pixelgrouping in an input pattern. Such systems offer flexible, easilyimplemented and relatively low cost solutions to a variety of tasksinvolving image recognition