The effectiveness of residue code checking for on-line errordetection in parallel two's complement multipliers has up to now onlybeen evaluated experimentally for few architectures. In this paper aformal analysis is given for most of the current multiplication schemes.Based on this analysis it is shown which check bases are appropriate,and how the original scheme has to be extended for complete errordetection at the input registers and Booth recording circuitry. Inaddition, we argue that the hardware overhead for checking can bereduced by approximately one half if a small latency in error detectionis acceptable. Schemes for structuring the checking logic in order toguarantee it to be self-testing, and thus achieve the totallyself-checking goal for the overall circuit, are also derived
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