A cache protocol for error detection and recovery in fault-tolerantcomputing systems

摘要

We propose an error detection and recovery protocol for redundantprocessor systems employing caches. The protocol allows cache-basedsystems to vote more often and thereby reduce the chance of losingsynchronization. The scheme is based on cache data broadcasting of adirty line after modification. The scheme effectively exploits theredundancy of a fault-tolerant system using hardware voting. It recoversfrom erroneous data written by a processor and this remedies theinsufficiency of error-correcting codes. The protocol can also be usedto speed-up resynchronization process for a temporarily failed processorin a redundant system. More than 60% of cache lines are fully coveredfor recovery due to errors originated from the cache itself, includingunrecoverable ECC errors. The performance overhead is to broadcast only2-3% of the total memory references