Design of a CMOS ASIC chip featuring analog neural computationalprimitives

摘要

An ASIC analog chip which implements the basic computationalprimitives of a neural model with on-chip learning has been designed andfabricated using a 1.5 μm CMOS technology. The chip contains about 3K transistors arranged into a matrix of 8×4 synapses fullyconnected to 4 neurons. Using the chip as basic module, it is possibleto obtain more complex networks. The adaptive architecture hosted by theanalog continuous-time CMOS VLSI circuits has been devised to supporthigh-level neural computational models (e.g. back propagation). Formalvariables of the algorithm are translated into electrical ones. Neuralcircuits feature a full analog and adaptive behaviour, and directly mapinto hardware the basic neural computational primitives. Analog adaptiveneural computation does not require high computational accuracy. Itsimplementation through full custom circuits is attractive, as it isefficient and compact