In recent years, domino logic circuits have received muchattention as high-speed circuits by taking the place of static CMOScircuits. However, in case of standard domino logic, only non-invertinggates are allowed. Then, clock-delayed (CD) domino logic that providesany logic function is proposed in order to overcome domino's drawback Inaddition, domino circuits are more sensitive to circuit noises comparedwith static CMOS circuits. In particular, crosstalk can induce criticalproblems. Therefore, we focus our attention on faulty operations inducedby crosstalk in CD domino circuits and propose a new fault simulationmethod We realize CD domino logic in VHDL and simulate on a VHDLsimulator. We performed experiments for the combinational part of somebenchmark circuits of ISCAS'89. And fault coverage for random vectorswas obtained from s27 to s1494 under the limitation of simulation time
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