METHOD AND APPARATUS FOR AUTOMATIC FAULT DIAGNOSIS OF ELECTRICAL CIRCUITS EMPLOYING ON-LINE SIMULATION OF FAULTS IN SUCH CIRCUITS DURING DIAGNOSIS

摘要

1428944 Testing logic circuits GENERAL RADIO CO 20 Aug 1974 [19 Feb 1974] 36558/74 Heading G1U A method of testing a logic circuit comprises the steps of:- (a) applying a sequence of test words to the circuit under test and comparing its outputs with the expected outputs, (b) upon detection of a disagreement between the actual output and the expected output stopping the sequence of test words and extracting from a partial fault dictionary a list of potential faults any one of which could have resulted in the observed disagreement, (c) for each potential fault, simulating a circuit of the type under test that includes the fault, and comparing its output in response to further words of the test sequence with those produced by the circuit under test in response to further words of the test sequence. Thus, the inventive method is a combination of the two known methods, namely (1) using a complete fault dictionary - which requires an enormous store - and (2) simulating for each circuit under test all possible faults - which is time consuming - and according to the Specification by a judicious mixture of these two methods significant savings in time and equipment can be achieved whilst still identifying about 90% of the faults in circuits found to be faulty. The Specification includes high level block diagrams showing how the method may be implemented, and a general discussion of the problems of testing large scale integrated logic circuits.