首页> 外文会议>Electron Devices Meeting, 1985 International >A sub-200 picosecond GaAs sample-and-hold circuit for a multi-gigasample/second integrated circuit
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A sub-200 picosecond GaAs sample-and-hold circuit for a multi-gigasample/second integrated circuit

机译:200皮秒以下GaAs采样保持电路,用于每秒数千兆采样的集成电路

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We report initial results on a digital/analog, 1-micron gate GaAs MESFET IC whose purpose is to record with bandwidths exceeding 1 GHz nonrepetitive analog transient waveforms of a few nanoseconds duration. Specialized buffered-fet logic digital circuits with Tpdas low as 70 psec generate a pulse burst that strobe a series of 20 linear gate sample-and-hold circuits. These 3-gate MESFET sampling circuits have demonstrated sampling apertures of less than 200 psec, without pretriggering required. Backgating effects on the circuit design and performance and high speed techniques are reviewed. Earlier work (1) on this scheme has been extended from 1nsec step inputs to 100 psec and variable biasing in the linear gate circuit has been added.
机译:我们报告了数字/模拟,1微米栅极GaAs MESFET IC的初步结果,其目的是记录带宽超过1 GHz的持续时间为几纳秒的非重复模拟瞬态波形。 T pd 低至70皮秒的专用缓冲逻辑逻辑数字电路会产生脉冲串,该脉冲串会选通一系列20个线性门采样保持电路。这些3栅极MESFET采样电路已经证明了小于200 psec的采样孔径,而无需进行预触发。回顾了电路设计,性能和高速技术对背景的影响。此方案的早期工作(1)已从1nsec阶跃输入扩展到100 psec,并在线性门电路中添加了可变偏置。

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