Comparative Evaluation of Multicore Dataflow DSPs with Different Arithmetic Units

摘要

DSPs and accelerators using FPGA technology and dataflow approach offer the potential for high performance in many applications including IoT-connected consumer electronics and so on. A dataflow approach provides the potential for exploiting parallelism inherent in programs. In our laboratory, we have developed a ring interconnected multicore dataflow DSP called LSC-Based DSP. In this work, we design five different kinds of arithmetic units including adder-subtractor, multiplier and divider. We implement LSC-Based DSPs with five different arithmetic units on an FPGA and evaluate them by comparison with both the logic resource usage and the execution time.