You have all spent weeks or months of onerous manual effort, from writing assertions to running long simulations (with limited success for corner-case bugs) or debugging false positives. This tutorial will give you a unique hands-on experience on how to detect and localize difficult bugs automatically, in just a few hours, during pre-silicon verification and post-silicon validation. We present the Quick Error Detection (QED) technique for post-silicon validation and debug. QED drastically reduces error detection latency, the time elapsed between the occurrence of an error caused by a bug and its manifestation as an observable failure. Symbolic QED combines QED principles with a formal engine for both pre- and post-silicon validation. Results from several commercial designs demonstrate: 1. For billion transistor-scale designs, you can now detect and localize difficult logic design bugs automatically (without having to write design-specific assertions) in only a few (~3) hours during presilicon verification. 2. You can now drastically improve error detection latencies of post-silicon validation tests by up to 9 orders of magnitude for quick debug, from billions of clock cycles to very few clock cycles, and simultaneously improve bug coverage. 3. You can now automatically localize bugs in billion transistor-scale designs during post-silicon debug, e.g., narrow locations of electrical bugs to a handful of flip-flops (~18 for a design with ~1million flipflops), in only a few (~9) hours. QED and Symbolic QED are effective for logic design bugs and electrical bugs inside processor cores, hardware accelerators, and uncore components such as cache controllers, memory controllers, interconnection networks or power management units. QED techniques have been successfully used in industry.
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