首页> 外文会议>IEEE Symposium on VLSI Technology >First demonstration of ∼3500 cm/V-s electron mobility and sufficient BTI reliability (max Vov up to 0.6V) In0.53Ga0.47As nFET using an IL/LaSiOx/HfO2 gate stack
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First demonstration of ∼3500 cm/V-s electron mobility and sufficient BTI reliability (max Vov up to 0.6V) In0.53Ga0.47As nFET using an IL/LaSiOx/HfO2 gate stack

机译:使用IL / LaSiOx / HfO2栅叠层首次展示了约3500 cm / V-s的电子迁移率和足够的BTI可靠性(最大Vov高达0.6V)In0.53Ga0.47As nFET

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In this paper, we demonstrate for the first time an implant free InGaAs n-MOSFET that meets the reliability target for advanced technology nodes with a max operating V of 0.6 V. In addition, an excellent electron mobility (μ=3531 cm2/V-s), low SS=71 mV/dec and an EOT of 1.15 nm were obtained. We also report the scaling potential of this stack to 1nm EOT without loss of performance, reliability and further reduction of the sub-threshold swing (SS=68mV/dec). On top of the novel IL we presented last year, in this paper we insert a LaSiO layer between the IL and HfO offering an increased chemical stability of the gate stack. This combination is key and offers both an improved interface quality as well as a reduction of the oxide trap density.
机译:在本文中,我们首次展示了无植入式​​InGaAs n-MOSFET,该器件满足最高工作电压为0.6 V的先进技术节点的可靠性目标。此外,其出色的电子迁移率(μ= 3531 cm2 / Vs) ,获得低SS = 71mV / dec和EOT为1.15nm。我们还报告了该堆栈在不降低性能,可靠性和进一步降低亚阈值摆幅(SS = 68mV / dec)的情况下可扩展至1nm EOT的潜在规模。在我们去年提出的新型IL的基础上,本文在IL和HfO之间插入LaSiO层,从而提高了栅堆叠的化学稳定性。这种结合是关键,不仅可以提高界面质量,还可以降低氧化物陷阱的密度。

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