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Evaluation of strength tests of Cu TSV chips using acoustic emission method

机译:用声发射法评估铜TSV芯片的强度测试

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The purpose of this study is to evaluate the strength of TSV silicon chips using a point-load on elastic foundation (PoEF) test, associated with an acoustic emission (AE) method for detecting local material cracks or delamination occurring during the test before the chip breaking (or catastrophic failure). The results indicate that there are no larger-than-25 dB AE signals and no via cracks occurring before the chip breaking. However, the delamination between copper cap and silicon dioxide surface (due to poor adhesion), and bond pad crash on loading contact were found occurring with 50 dB of AE signals, respectively. It has been concluded that the strength of TSV chip is governed by the via interfacial crack failure occurring right at the maximum load.
机译:这项研究的目的是使用弹性基础上的点载荷(PoEF)测试结合声发射(AE)方法来评估TSV硅芯片的强度,该方法用于检测芯片测试前在测试过程中发生的局部材料裂纹或分层破坏(或灾难性的失败)。结果表明,在芯片断裂之前,没有大于25 dB的AE信号,也没有发生过孔裂纹。然而,发现铜盖和二氧化硅表面之间的分层(由于不良的粘附力)以及负载接触时的焊盘击穿分别发生在50 dB的AE信号下。已经得出结论,TSV芯片的强度受恰好在最大负载下发生的通孔界面裂纹破坏的支配。

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