Accelerating and deceleratingmin-sum-based gear-shift LDPC decoders

摘要

Low-Density Parity-Check (LDPC) decoders typically implement a single decoding algorithm or update rule, which narrows down the design space of the decoder and maintains its overall simplicity. However, gear-shift techniques combine multiple decoding algorithms, update rules and quantization of the log-likelihood ratios (LLRs), allowing wider design space explorations as more parameters can be fine-tuned to a particular need. Gear-shift LDPC decoders have been shown to improve both the decoding throughput and the energy efficiency per bit decoded, while achieving similar capacity compared to traditional approaches that only use one algorithm. In this paper, we incorporate gear-shift techniques based on the Min-Sum algorithm (MSA) and Self-Corrected Min-Sum algorithm(SCMSA) using variable quantization steps. The proposed design allows bit error rate (BER) performances close to themore powerful SCMSA running only a selected number of iterations using the most powerful update rule.