Design of a floating-type impedance scaling circuit for large capacitances

摘要

Impedance scaling technique is known as a method to reduce chip area of large capacitances for low frequency integrated filters. The conventional technique realizes only grounded low impedance components. This paper proposes a construction of a floating-type impedance scaling circuit. The proposed circuit can be applied to various low frequency analog circuits. The validity of the proposed circuit is confirmed by simulation of a biquad filter employing the proposed circuit.