Lab-on-chip is a very promising point-of-care technology, where the specimen is placed directly on a CMOSchip for imaging without the use of any labels or chemicals and with no intervening optical components.However, lab-on-chip technologies developed so far have been limited by the existing pixel size of CMOS imagesensors. To be able to accurately resolve small biological samples, the sensor pixel size must be less than thesize of the object under examination. For example, bacteria range from 500nm to 5μm and viruses from 30nm to300nm and thus require image sensors with nanoscale dimensions. However, reducing the size of an image sensoris challenging. Light sensitivity greatly reduces at and below the optical diffraction limit due to increasinglypoorer coupling. In addition, CMOS image sensors typically use a refractive microlens that will not scale dueto diffraction limits below around 1.4 μm. Further, conventional colour filters are made of absorptive dyes orpigments that do not work at nanometer thicknesses.A promising alternative approach to break this size barrier involves the use of nanoscale apertures in metalfilms to produce localized plasmon resonances. For example, investigated strategies for addressing the fabricationchallenges in submicron RGB plasmonic pixels and demonstrated successfully working pixels at 1.4 μm. Veryhigh transmission rates of up to 90% have been reported from an array of annular apertures based on localizedsurface plasmons. Our work is exploring a path to nanophotonic pixel technology in which pixels will be madeup of plasmonic pixels with one single 40-60 nm double coaxial hole integrated onto submicron CMOS pixels of120nm. As the pitch of the nanophotonic pixel array is ultimately set by the CMOS pixel pitch, this paperwill focus on the design considerations limiting this geometry.CMOS image sensors offer low cost, low power and a potentially high level of integration. In this context,CMOS sensors almost universally use a pinned photodiode technique, first developed over 20 years ago, due toits inherently low noise, high quantum efficiency and low dark current. This is typically combined with anctive pixel sensor" (i.e., per-pixel voltage follower) circuit and back-side illumination (with substrate thinning)for greatly improved performance. A major constraint to down-scaling the photodiode in a CMOS sensor isthat a reasonable image quality requires in the order of 3000 electrons in the well to be available to interactwith the incoming photons. The noise level will inevitably increase as the photodector size decreases. Asa result, a careful trade-off is required between spatial resolution and dynamic range while ensuring that theshot-noise limited SNR remains adequate. In a pinned diode circuit the full well charge can be approximatedby: Q_(FW) = C_(PPD)(V_P-V_(TG)); where C_(PPD) is the average diode capacitance, V_P is the pinning potential, VTGis the photodiode saturation voltage which is a logarithmic function of I_(d0), determined by the width and lengthof the transfer transistor. VP becomes increasingly difficult to estimate as pixel size reduces, and thus 3D TCADis typically used to explore the circuit operation. At the same time, the diode geometry must be arranged tomaximize the value of C_(PPD). Further, for small pixels the transfer time (out of the diode well) is proportionalto l~3 , where l is the transfer distance, mandating a high performance data acquisition system and additionaloff-chip signal processing.Fully depleted silicon on insulator (FDSOI) processes have proved to be simpler to make than the equivalentbulk processes and may become a preferred option in advanced nodes below 20nm. Various hybrid bulk/SOIpixel structures have been proposed to address this issue. For example, both and describes a SOI CMOSactive pixel image sensors where the pinned photodiode, oating diffusion and transfer gate were fabricated onthe handle wafer while the reset and source follower circuits were built on the seed wafer. In this way, thephotodiode could be optimized for quantum efficiency and low dark currents independently of the other circuitsalthough the resulting pixel was still quite large (around 20μm × 20μm). However, in previous work, theprocess was able to be optimized in ways that suited the application. We aim to achieve a similar result using astandard process that could support conventional analogue and digital components on the same chip.Our proposed pixel structure is outlined in Fig. 1 (adapted from and), which combines a number ofexisting techniques to achieve a pixel with active dimensions in the order of 100-120nm. It can be seen fromthis sketch that the key restriction to sub-100nm pixel sizes in this technology is still the size of the p~-/p~+pinned diode in the handle wafer, identical to the limitations for the same structures in bulk. For example, wehave conducted our experiments in a commercial 28nm UTBB-FDSOI process for which the minimum n-wellsize is 80nm~2. The additional clearances required by the design rules mandates an absolute minimum pixel sizeof ～710nm square. Adding the reset and readout transistors implies a pixel pitch of around 1 micron, still toolarge for the eventual application. Bulk processes down to 16nm and SOI processes to 22nm are commerciallyavailable at this time. However, as n-well scaling is never proportional to gate length, these more aggressivetechnologies will, at best, reduce the pixel size to above 500nm, still too large for this application.Thus, although ultra-thin body FDSOI offer a compelling opportunity to optimize the design of the diodein the handle wafer separately to the various support transistors in the film, it is clear that this methodologycannot achieve a suitable sub-micron pixel pitch, even at the smallest technology nodes currently available.On the other hand, while FDSOI offers many advantages including high performance, low leakage and thestraightforward integration of mixed signal applications (digital/analog/RF), developing image sensor structuresin the silicon film (above the body oxide) is more problematic as the optically transparent thin film can resultin low quantum efficiency. As a result, on-chip signal processing will be necessary to improve the signal to noiseratio of the sensor. This will be the objective of our future work.
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