Power dissipation in one-latch and two-latch double edge triggeredflip-flops

摘要

In the paper new implementations of double edge-triggered (DET)flip-flops using one latch are presented. In the proposed circuits dataare sampled into the latch during a short transparency period for eachedge of the clock signal. Three implementations (dynamic, semi-staticand static) of the one-latch DET flip-flop are presented and comparedwith standard two-latch DETs. SPICE simulations of power dissipation asa function of the switching activity of input signal are presented.One-latch DETs have reduced transistor count and lower power dissipationwith respect to previously reported DET flip-flops. Power saving isrelevant when an array of flip-flops share a single clock driver and forlarge input signal transition probability