Development of Parallel-to-Serial and Serial-to-Parallel Converters for Debugging Large-Scale AQFP Logic Circuits

摘要

Adiabatic quantum-flux-parametron (AQFP) logic is anemerging technology in superconducting electronics thatshows promise towards building extremely energy efficientcomputing systems with bit energies approaching 100kBT. In the effort of building an AQFP-basedmicroprocessor, we have developed a prototype reducedinstruction set computer (RISC)-based architecture calledMANA (Monolithic Adiabatic iNtegration Architecture). In order to build and demonstrate the MANA chip, weare faced with the constraints of fitting the entire design ona 10 mm × 10 mm chip using the AIST 10 kA/cm~2 highspeedstandard process (HSTP). With this consideration,we have configured MANA with a 4-bit data word size anda 12-bit instruction word size. Under this configuration, weestimate that a total of 20,000 Josephson junctions (JJs) areneeded to implement this demonstrator chip.