Modelling and performance analysis of digital baseband processor ofthe GPS receiver

摘要

A global positioning system (GPS) receiver has been modelled andimplemented in software. A digital full-time delay lock loop (DDLL) isdesigned for the pseudorange time delay measurement and a digitalphase-locked loop (DPLL) is applied for measurements of the carrier beatphase and Doppler shift. The closed form expressions of the detectionand false-alarm probabilities for the code phase acquisition process andthe variance of the code phase tracking error for the code phase finesynchronization process are derived. The performance of the modelledstatic receivers is validated by computer simulations