首页> 外文会议>Personal, Indoor and Mobile Radio Communications, 1992. Proceedings, PIMRC '92., Third IEEE International Symposium on >Modelling and performance analysis of digital baseband processor of the GPS receiver
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Modelling and performance analysis of digital baseband processor of the GPS receiver

机译:GPS接收机数字基带处理器的建模与性能分析

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A global positioning system (GPS) receiver has been modelled and implemented in software. A digital full-time delay lock loop (DDLL) is designed for the pseudorange time delay measurement and a digital phase-locked loop (DPLL) is applied for measurements of the carrier beat phase and Doppler shift. The closed form expressions of the detection and false-alarm probabilities for the code phase acquisition process and the variance of the code phase tracking error for the code phase fine synchronization process are derived. The performance of the modelled static receivers is validated by computer simulations.
机译:全球定位系统(GPS)接收器已建模并通过软件实现。数字全时延迟锁定环(DDLL)设计用于伪距时间延迟测量,数字锁相环(DPLL)用于测量载波拍频和多普勒频移。推导了码相位获取过程的检测概率和虚警概率以及码相位精细同步过程的码相位跟踪误差方差的封闭式。通过计算机仿真验证了建模的静态接收器的性能。

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