Standard CMOS implementation of a multiple-valued logicsigned-digit adder based on negative differential-resistancedevices

摘要

This paper presents MOS-NDR, a new prototyping technique formultiple-valued logic circuits combining MOS transistors and multipeaknegative differential-resistance (NDR) devices such asresonant-tunneling diodes (RTDs). MOS-NDR emulates the foldedcurrent-voltage characteristics of NDR devices such as RTDs using onlyNMOS transistors, MOS-NDR has enabled the development of a fullyintegrated multivalued signed-digit full adder (SDFA) circuit by meansof a standard 0.6-micron CMOS process technology. The prototype has beenfabricated and correct operation has been verified. The circuitdimensions are 123.75 by 38.7 microns, which is more than 15 timessmaller than the area required by the equivalent hybrid RTD-CMOSprototype. The propagation delay of the hybrid RTD-CMOS design isestimated to be close to six times higher than that of the MOS-NDRimplementation