A data path synthesis method to self-testable application specificintegrated circuit (ASIC)

摘要

Allocation is the High Level Synthesis task that reaches a datapath definition obeying hardware restriction and optimizing the chiparea and performance. Testability is a sequence of procedures thatensures that an ASIC is working correctly. Self-Testability is the casewhere the whole test procedure is implemented in the chip. A design issaid full testable when, in the test mode, all the possible faults canbe detected. This paper presents a method to consider theself-testability of the ASIC during the allocation process. A few otherthan the usual hardware restrictions are imposed to ensures theself-testability. The achieved data path will be self-testable and willhave the smallest possible area. Usually, this kind of optimizationproblem is NP-Complete. In our case, heuristics are used to reach a goodsolution in an acceptable computing time. This paper shows theheuristics used in our allocation algorithm and a case of study, thatvalidates the whole process, is shown