Exploiting FPGA-based architectures and design tools for problemsof reconfigurable computations

摘要

This paper addresses the design and implementation of aconfigurable “combinatorial processor”, a computationaldevice, which can be used for solving different combinatorial problems.These can be characterized by a set of variables having a limited numberof values with a corresponding set of operations that might be appliedto these variables. Different mathematical models can be used todescribe such tasks. We adopted a matrix representation, which is easierto treat in digital devices. The operations on discrete matrices areunique and cannot be efficiently performed on a general-purposeprocessor. Although the number of such operations grows exponentiallywith the number of variables, to solve a particular combinatorialproblem a very small number of such operations is usually required.Hence the importance of providing for the dynamic change of operations.The paper presents an approach allowing the run-time modification ofcombinatorial computations via reloading the RAM-based configurablelogic blocks of the FPGAs