An asynchronous transfer model (ATM) switch which has lowerhardware complexity than that of the output queuing switch is presented.The reduction in the hardware complexity is obtained without eitherlosing the self-routing property or suffering from performancedegradation under nonuniform traffic patterns. The switch consists ofshift networks that are interconnected with distributors in two stages.Introducing the distributor between the stages of shift networks allowsof packets to be distributed evenly to all the input ports of shiftnetworks in the following stage. Although the switch becomes blocking,it retains the self-routing property and achieves the maximum throughputof 100% with only a small additional delay
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