Bit-serial pipeline synthesis for multi-FPGA systems with C++design capture

摘要

Developing applications for a large-scale configurable systemcomposed of state-of-the-art FPGA technology is a grand challenge. FPGAsare inherently resource limited devices in terms of logic, routing, andIO. Without a careful circuit implementation strategy, one would waste alarge portion of the potential capacity of the configurable hardware.Also, high-level design entry support is essential for such large-scalehardware. A C++ design tool has been implemented which maps thecomputational algorithms onto bit-serial pipeline networks which exhibithigh performance and maximize the device utilization of each FPGA. Withthis tool, the designer is able to develop applications in a very shorttime, and also is able to try out different algorithm implementationseasily to see the trade-offs in terms of performance and hardware sizeinstantaneously. Based on this C++ design tool, a number of DSPapplications such as 1D and 2D filters, adaptive filters, InverseDiscrete Cosine Transform, and digital neural networks were designed