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Investigation of ESD Performance in Silicon Integrated Passive Devices

机译:硅集成无源器件中的ESD性能研究

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ESD failure limits have been measured in a variety of silicon integrated passive devices using the Human Body Discharge Model. The failure mechanism for these circuits is typically the destructive breakdown of the thin insulator layer in metal-insulator-metal capacitors. The capacitors in this particular technology have a static breakdown of 70 to 100V. Failure from ESD events for a single capacitor typically occurs for voltages of 200 to 300V. Tests of more complex circuits show that the ESD performance is extended by using series arrangements of capacitors. In some circuit types it is possible to use inductive shunt protection. This has been found to increase the failure voltage to above 3KV, which was the limit of the test equipment.
机译:已使用人体放电模型在各种硅集成无源设备中测量了ESD故障极限。这些电路的故障机制通常是金属-绝缘体-金属电容器中绝缘体薄层的破坏性击穿。此特定技术中的电容器具有70至100V的静态击穿电压。单个电容器的ESD事件导致的故障通常发生在200至300V的电压下。对更复杂的电路进行的测试表明,通过使用电容器的串联布置可以扩展ESD性能。在某些电路类型中,可以使用电感分流保护。已经发现,这会将故障电压增加到3KV以上,这是测试设备的极限。

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