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A flexible 12-bit self-calibrated quad-core current-steering DAC

机译:灵活的12位自校准四核电流控制DAC

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This paper presents a flexible fully integrated self-calibrated quad-core 12-bit current-steering 180nm CMOS DAC. Its novel architecture features multiple parallel sub-DAC unit cores. Their various combinations deliver smart flexibility in: performance, functionality, power management, design reuse, and smartness. The parallel sub-DAC units can be used together or separately to optimize the performance of a targeted mixed-signal application. Unused sub-DAC units can be switched off to optimize the power consumption. The new parallel sub-DACs architecture facilitates a new calibration algorithm. This algorithm together with small calibrating DACs and a current comparator enables the realization of the first fully integrated self-calibration start-up method that corrects the mismatch errors of all binary and unary current sources. The presented self-calibrated flexible DAC achieves measured linearity of better than 12-bit, while occupying small silicon area due to the intrinsic 9-bit accuracy of the DAC unit core.
机译:本文提出了一种灵活的,完全集成的自校准四核12位电流控制180nm CMOS DAC。其新颖的架构具有多个并行子DAC单元内核。它们的各种组合在以下方面提供了灵巧的灵活性:性能,功能,电源管理,设计重用和灵巧性。并行子DAC单元可以一起使用,也可以分开使用,以优化目标混合信号应用的性能。可以关闭未使用的子DAC单元以优化功耗。新的并行子DAC架构促进了新的校准算法。该算法与小型校准DAC和电流比较器一起实现了第一个完全集成的自校准启动方法,该方法可以校正所有二进制和一进制电流源的失配误差。由于DAC单元内核固有的9位精度,因此所提出的自校准柔性DAC的实测线性度优于12位,同时占用的硅面积较小。

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