Design and analysis of high performance pulse ring VCO

摘要

This paper presents a low phase noise, low power, wide tuning range, small area pulse ring oscillator fabricated in inexpensive 130nm CMOS technology. The ring uses very non-linear Pulse gates instead of conventional inverters as buffers substantially reducing the impulse sensitivity function (ISF) and thus the phase noise. The timing signal is rising-edge and ground referenced, allowing the supply to be used as control voltage. 6dB phase noise improvement is projected in ISF based phase noise simulation over a same frequency ring oscillator. Fabricated ring oscillators show a phase noise of -97.46 dBC/Hz at 1MHz offset for 1.889GHz oscillator at 2.94mW power consumption and -95.13 dBC/Hz at 1MHz offset for 897MHz oscillator at 617uW power consumption. The oscillators have a tuning range of 513MHz to 2.64GHz. Figure of merit of the design shows a better performance than any other non phase locked voltage controlled ring oscillator.