Design of high-performance VCOs for communications.

摘要

Voltage-controlled oscillators (VCO) are important building blocks for phase-locked loops (PLL). The random fluctuations in the output phase of the oscillator, in terms of jitter or phase noise, are extremely undesirable in most applications. The VCO is a major contributor to the PLL phase noise at frequencies outside its loop bandwidth.; This thesis presents a phase noise modelling framework for CMOS ring oscillators. The analysis considers both the linear and nonlinear operations. It indicates that fast rail-to-rail switching has to be achieved to minimize phase noise. Also the flicker noise in the bias circuit can potentially dominate the phase noise at low offset frequencies. Therefore; for narrow bandwidth PLLs, noise up conversion from the bias circuits should be minimized. We define the effective Q factor (Q_eff) for ring oscillators and predict its increase for CMOS processes with smaller feature sizes.; The digital switching noise coupled through the power supply and substrate is usually the dominant source of clock jitter on a mixed-signal chip. This thesis analyzes the impact of the supply and substrate noise on the oscillator phase noise, and suggests that increasing the signal swing is also an effective way of reducing the jitter due to the supply and substrate noise.; We have also analyzed ring oscillators with memory delay cells. It is shown that the jitter can be reduced by introducing a proper amount of memory into the delay cells.; We have designed oscillators in various CMOS technologies. Our phase noise model has been verified by the measurement results. Based on our understanding of phase noise, we have designed a two-stage ring VCO with differential control and quadrature outputs. The measured common-mode noise rejection at 1MHz is 32dB better than for a single-ended control topology. The measured phase noise is −117dBc/Hz at a 1MHz offset from the 973MHz center frequency. We have also designed a PLL with a ring oscillator based on the above design. It is fabricated in a 0.25μm CMOS technology. Some measurement results are presented in this thesis.