UVM based Controller Area Network Verification IP (VIP)

摘要

As the complexity of System on Chip(SOC) designs is increasing day by day, verification is becoming a complex task to attain. A SOC design consists of various intellectual property cores (IP). To verify so many IPs, a complex testbench has to be developed which is not an easy task to achieve. So to make the verification an easy task, Verification Intellectual Property cores (VIP) are developed. In this paper, the design of the Controller Area Network (CAN) VIP is proposed. This VIP is developed using SystemVerilog based universal verification methodology (UVM. The test environment of this VIP is verified by running appropriate test cases. The coverage is collected based on the test cases to verify whether the functional specifications of the CAN protocol are covered or not. This VIP is simulated using Cadence Xcelium tools to check the effectiveness of the proposed approach.