A 20 Gb/s Latency Optimized SerDes Transmitter for Data Centre Applications

摘要

The throughput and the latency for practically larger capacitive loads are the two key factors that needs to be considered in the HPC (High Performance Computing), AI (Artificial Intelligence), high frequency trading applications. In this paper we are addressing the latency which needs to be low for any such applications. For this implementation we have re-looked into the functionality of each constituents of the transceiver and implemented the circuits to reduce the overall latency of the system without affecting the Serializer/Deserializer (SerDes) throughput. The proposed architecture replaces some of the conventional blocks of transceivers to reduce the latency. In this paper we describe the implementation in detail with circuit simulated upto extracted netlist level. This design of a transceiver with 20gb/s is sent for fabrication in TSMC 28nm HPC+ technology node. This paper is limited to transmitter portion of the work, where we see a major reduction in the associated latency compared to conventional transmitters.