A Stream Hardware Architecture for Keypoint Matching Based on a Speculative Approach

摘要

Detection, description, and matching of keypoints are commonly used as a first step in embedded real-time vision applications such as tracking, 3D reconstruction, visual odometry, or SLAM. In this paper, we present a hardware accelerator for keypoint extraction and matching designed to meet low latency and memory footprint constraints while being scalable and generic. Different pipelines with Harris detector and U-SURF descriptor have been implemented on FPGA targets. Our temporal matching pipeline implementation reaches up to 320 fps at 100 MHz on a Xilinx ZYNQ XC7Z020 for VGA images with less than half an image of latency.