Partial Ternary Full Adder versus Complete Ternary Full Adder

摘要

This paper explores whether or not a complete ternary full adder, whose input variables can independently be ‘0’, ‘1’, or ‘2’, is indispensable in the arithmetic blocks of adder, subtractor, and multiplier. Our investigations show that none of these arithmetic units require a complete ternary full adder. Instead, they can be designed by means of partial ternary full adder, whose input carry never becomes ‘2’. Therefore, ternary adders can be realized with fewer transistors and higher performance. Afterwards, three well-known complete ternary full adders are changed into partial versions. Simulation results show considerable improvements for the partial ternary full adders over the complete versions.