A Fast Locking 5.8 – 7.2 GHz Fractional-N Synthesizer with Sub-2 us Settling Time in 22 nm FDSOI

摘要

This paper presents a fast settling all-digital fractional-N synthesizer that employs efficient frequency tuning word estimation with type-I and type-II loop settling. It is combined with a DCO with a highly linear coarse tuning bank allowing wide-band closed-loop operation. Linear frequency hopping prediction is used, followed by a series of type-I recovery phases to compensate for drifts and digital zero-phase resets to reduce phase transients due to type-I settling. The DCO gain is equalized by exploiting routing inductance and employs a hybrid binary-thermometric segmentation in a 5.8–7.2 GHz range. The circuit was processed in a 22 nm FDSOI technology and achieves a settling time below 2 μs in a 200 MHz hopping range. The synthesizer has an integrated phase noise of 115 fs with −108 dBc/Hz in band phase noise and 31 mW power consumption resulting in a −243.9 dB FOM.