Implementation of Multimedia System-on-Chip in Field Programmable Gate Array Device

摘要

The consumer, hand-held and other electronic devices are typically very rich in multi-media capabilities today. Thanks to under-the-hood System-on-Chip devices, which are making this possible. With exponentially shrinking silicon manufacturing process geometries, it is possible to pack more and more functionality into tiny System-on-Chip devices. However, typical development cycles of such System-on-Chip devices are too long and the market opportunity window is relatively short. Moreover, apart from huge development costs, System-on-Chip devices carry the risk of re-spins. Further, re-spin not only causes additional costs but also delays the product launch. Hence, for time-to-market critical products, it may be worthwhile to consider alternate options, wherever feasible. One of the alternate low-risk options is using a Field Programmable Gate Array device in realizing intended System-on-Chip functionality. This especially makes sense, when the expected product volumes are not very high and per-device cost and power dissipation are not prohibitively high. Hence, it is a trade-off between product volumes, development cycle time, development cost, per-device cost and device power dissipation. When the product volumes are very high, developing System-on-Chip device using custom silicon is an obvious choice. That will result in the best per-device cost and lowest power dissipation. In addition, wherever product volumes are low-to-medium, realizing System-on-Chip in Field Programmable Gate Array device is a choice. That is expected to result in a very short development cycle, low development cost and low risk, even at the expense of higher per-device cost and power dissipation. This paper highlights implementation aspects and challenges of realizing a Multimedia System-on-Chip in a Field Programmable Gate Array Device.