Pipelined MIPS Simulation: A plug-in to MARS simulator for supporting pipeline simulation and branch prediction

摘要

This paper presents the design and implementation of a Microprocessor without Interlocked Pipeline Stages (MIPS) pipelined simulator build on top of the MIPS Assembler and Runtime Simulator (MARS) as a plug-in. The MARS Simulator is a lightweight interactive development environment (IDE) for programming in MIPS assembly language, intended for education-level use. This plug-in called “Pipelined Simulator and Branch Explainer (PBSE)” provides the MARS users with the ability to simulate a pipelined processor execution of MIPS assembly instruction which the original MARS simulator does not support. The tool also provides additional functionality as such Branch Prediction. With the use of the plug-in, MARS users can better analyze the assembly codes executed in a pipelined processor with branch prediction and improve their understanding of Computer Architecture.