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Fault Resistant 8-Bit Vedic Multiplier Using Repairable Logic

机译:使用可修复逻辑的抗故障8位吠陀乘法器

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In the present scenario with the high frequency use of arithmetic and logic units in significant applications like data transmission, data processing and many, accuracy plays a crucial role. Hence fault resistant circuits have been recent topic of research. This paper comes under the similar journal producing a fault resistant 8 Bit Vedic Multiplier that is build using fault resistant logic gates. At any case the output of this circuit is completely reliable as it avoids the maximum possible soft faults. In the presence of fault, repair signal is introduced to provide the truthful output. This is achieved at a cost of hardware duplication but the delay i.e the critical path remains same as that of the conventional circuit without fault tolerant or repair circuitry.
机译:在当前情况下,在诸如数据传输,数据处理等许多重要应用中频繁使用算术和逻辑单元,准确性起着至关重要的作用。因此,抗故障电路已经成为最近的研究主题。本文使用类似的日记本,其中介绍了使用抗故障逻辑门构建的抗故障8位Vedic乘法器。在任何情况下,该电路的输出都是完全可靠的,因为它避免了最大可能的软故障。在出现故障时,引入维修信号以提供真实的输出。这以硬件复制为代价来实现,但是延迟,即关键路径保持与没有容错或修复电路的常规电路相同。

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