A RISC-V Fault-Tolerant Microcontroller Core Architecture Based on a Hardware Thread Full/Partial Protection and a Thread-Controlled Watch-Dog Timer

摘要

The electronics devices that operate in the extreme space environment require a high grade of reliability in order to mitigate the effect of the ionizing particles. For COTS components this can be achieved using fault-tolerant design techniques which allow such design to fulfil the space mission requirements. This paper presents the design and the implementation of one of the Klessydra F03x microcontroller soft core family, called the F03_mini, which is a RISC-V RV32I compatible fault-tolerant architecture enhanced by a Hardware Thread (HART) full/partial protection and a thread-controlled Watch-Dog Timer module. The core architecture has been synthesized and implemented on an ARTIX-7 A35 FPGA and fault-injection by the meaning of a functional RTL simulation has been performed in order to evaluate the robustness to Single Event Effects (SEE). Experimental results are provided, illustrating the impact and the benefits obtained by the usage of the proposed TMR protection techniques as well as a thread-controlled Watch-Dog Timer.