A 2.4-GHz 500-µW 370-fsrms Integrated Jitter Sub-Sampling Sub-Harmonically Injection-Locked PLL in 90-nm CMOS

摘要

This paper proposes a sub-sampling (SS) sub-harmonically injection-locked (SI) PLL. Both the SS and SI techniques are incorporated to realize a low-jitter low-power PLL. To ensure both techniques operate coherently, the injection timing of the SI path is calibrated through the assist of the SS loop. Fabricated in a 90-nm CMOS, the proposed 2.4-GHz PLL consumes only 500 µW from a 1-V supply. With a 40-MHz reference frequency, this SS-SIPLL achieves 370-fsrms integrated jitter (10 kHz to 30 MHz); the FOM is -251.6 dB.